An Automated Reliability hancement Tool for Defect- Tolerance

Due to the expected rise in defect rate of devices in a nanotechnology based digital system, tools and techniques to build reliable architectures is gaining importance. In this paper, we propose an automated environment for reliability analysis and insertion of adequate redundancy for reliability enhancement. The input to this prescribed design flow is the architectural description of a non-redundant or reconfigurable logic network in EDIF (Electronic Design Interpretation Format used to exchange design data between CAD systems) that is partitioned into components and nets by automatic translation to a microarchitectural XML (MXML) representation, and a user preferred redundancy scheme is introduced. This MXML is translated to scripts that can be directly given as input to our NANOLAB or NANOSMART reliability/redundancy analysis tools. We are also developing a reliability analysis engine for serial TMR architectural configurations based on algorithms by Abraham et al. so that reliability results computed by this algorithm can be compared with the ones obtained from our tools. We expect such a design loop to ease and expedite the design space explorations for both combinational and sequential systems by eliminating need to incorporate new tools and aid integration of other CAD tools with our reliability analysis tools.